As feature sizes of metal-oxide-semiconductor (MOS) and complementary metal-oxide-semiconductor (CMOS) devices are reduced, the lateral electric field generated in MOS devices increases. A strong enough electric field gives rise to so-called “hot-carrier” effects in MOS devices. Hot-carrier effects cause unacceptable performance degradation particularly in MOS devices with short channel lengths, e.g., less than 0.5 μm. To overcome the hot carrier instability problems of MOS devices, MOS devices can be provided with shallow lightly doped source/drain regions that extend just to the gate electrode region and heavily doped source/drain regions that are laterally displaced away from the gate electrode region.
The lightly doped regions are used to absorb some of the potential into the drain and thus reduce the electric field. The field is reduced by the lightly doped regions because the voltage drop is shared by the drain and the channel, in contrast to a conventional drain structure, in which almost the entire voltage drop occurs across the channel region. The reduction of the electric field causes a reduction in hot carriers injected into a gate dielectric, which greatly increases the stability of the device.
The lightly doped source/drain regions are typically formed in the semiconductor substrate using the gate electrode and sidewall spacers as a mask during the lightly doped source/drain implantation. The sidewall spacers can be formed alongside the gate after the lightly doped source/drain implantation. The heavily doped regions can then be formed in the semiconductor substrate using the gate electrode and additional sidewall spacers laterally displaced from the gate electrode as a mask during the heavy dose source/drain implantation.
The sidewall spacers, which are used in the formation of the lightly doped regions, can be formed from materials, such as silicon nitride and silicon dioxide. Silicon nitride spacers are typically formed by first providing an oxide layer over the gate. The oxide layer functions as an etch stop during formation of the silicon nitride spacers. The oxide layer is typically provided by thermal oxidation processes, such as rapid temperature processing (RTP). A nitride conformal film can then be deposited over the gate, and the nitride film can be anisotropically etched by an etching process, such as plasma etching.
The thermal oxidation process used to form the oxide layer can potentially cause dopant migration or other unwanted effects in surrounding device areas. Dopant migration from the gate to the oxide layer can deplete dopant ions from the gate, which can adversely affect the electrical performance of the MOS device. For example, a MOS device in which dopant ions are depleted from the gate can have a higher resistance, lower carrier concentration, and lower drive current compared to a MOS device in which the dopant ions are not depleted from the gate.